Page History

----
{center}
!ExportedClocks.bmp!
*EXPORTED CLOCKS* Dialog
{center}
----
{excerpt}
* {blue:Enable}: Each clock can be enabled/disabled. (*CFG* setting)
* {blue:Phase Shift (us)}: Each clock signal can be phase shifted relative to the true start of frame/line/pixel. Only a positive phase shift (delay) is supported at this time. (*CFG* setting)
* {blue:Gate Active}: (Only settable for Line Clock at this time). Specifies that clock signal is 'gated' by the parent clock (frame->line and line->pixel are parent/child pairs). Gating is required to prevent clock ticks when acquisition is not active. The default settings should apply for most cases.
(i) When {blue:Gate Active} is selected, the {blue:Phase Shift} of the parent clock is added to the value for the child clock.
(i) Enabling {blue:Gate Active} for the Line Clock suppresses clock tick for final line if {blue:Discard Flyback Line} is enabled in the {report-info:data:Configuration|render=wiki|source=SI3.7 Data} panel. However, this prevents {blue:Phase Shift} values for Frame and Line clocks from being independent.

* {blue:Polarity}: Specifies if rising or falling edge signals the start of frame/line/pixel.
* {blue:Pixel Fraction}: Specifies at what fraction of the pixel period to generate the edge _not_ specified by the {blue:Polarity}. Value must be < 1, to allow edge specified by {blue:Polarity} to occur at start of subsequent pixel period. (*CFG* setting)

* {blue:Export Clocks on FOCUS}: If false, the clock signals are only generated during *GRAB/LOOP* acquisitions, not *FOCUS* acquisitions. (*USR* setting)

(/) Settings labeled as *CFG* settings are considered part of the ScanImage [Configuration|http://openwiki.janelia.org/wiki/pages/viewpage.action?pageId=8684238] and saved to CFG files. Different configuration files can save different values of this setting. This is useful, for instance, if you want the frame clock to be exported only for certain experiments, but not others. 
(/) Settings labeled as *USR* settings are considered part of ScanImage [User Settings|http://openwiki.janelia.org/wiki/pages/viewpage.action?pageId=8684424] and saved to USR files.

h4. Configuring Exported Clocks in INI File

Each clock output requires a National Instruments [counter/timer channel|http://zone.ni.com/devzone/cda/tut/p/id/9376#toc3] be used. These must be specified in the ScanImage [*INI*|SI_INIFile] file. 

Both Board and Counter ID values must be specified -- e.g. {vi-statevar:state.init.frameClockBoardID} &  {vi-statevar:frameClockCtrID} must be specified to enable frame clock feature, etc.

{info:title=Where to Connect?!}On older breakout boxes, you will find BNCs or terminals labelled directly as CTR0 OUT or CTR1 OUT. On newer breakout boxes, you won't find these. For all board series, the following applies: Ctr 0/1/2/3 map to PFI 12/13/14/15 respectively. Only X series boards have Ctr 2/3 channels.{info}

(i) Note that Ctr0 on the primary board ({vi-statevar:state.init.acquisitionBoardID}) is reserved by ScanImage, and not available for frame/line/pixel clocks

h4. Frame/Line/Pixel 'End' Edge
For the exported clock signals, the edge _not_ specified by {blue:Polarity} signifies the 'end' of each Frame/Line/Pixel. The timing/meaning of the 'end' is as follows:

* *Frame/Line Clocks*: The 'end' of Frame/Line occurs means acquisition has ended for current frame/line, while acquisition for new frame/line has not begun. This occurs at the start of the scanner flyback or turnaround time at end of line, or end of last line in frame.

* *Pixel Clock*: The Pixel clock handling is different because there are no gaps between pixel periods; thus the location of the 'end' edge must be user specified (via *Pixel Fraction*).

h4. DAQ Board Considerations



{tip}The Frame/Line/Pixel clock feature is most powerful with new [X series boards|http://www.ni.com/xseries/]. Future ScanImage versions may be able to get more functionality out of other/earlier board families, but this cannot be guaranteed as a development priority.{tip}

* Finite clock generation is only possible with [X series boards|http://www.ni.com/xseries/]. When using a non-X series board, additional clock 'ticks' may appear after acquisition is finished, because the counter output is actually stopped in software.

* Consequently, pixel clock generation -- which requires finite clock generation -- is only possible with [X series boards|http://www.ni.com/xseries/] at this time.

* [X series boards|http://www.ni.com/xseries/] have 4 counter/timer channels, while other board families have only 2 counter/timer channels
{excerpt}