• Created by Unknown User (iyerv), last modified on Jan 15, 2014
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Possible FPGA Changes

  1. handler

    Support multiple channels

    Priority MEDIUM
    iyerv
    Jan 15, 2014
  2. handler

    Support multiple channels (parallel processing of each channel; select which to include in output FIFO transferred to host)

    Priority MEDIUM
    iyerv
    Jan 15, 2014
  3. handler

    Allow host zero-copy reads by padding data as needed to ensure host FIFO is multiple of 2048 elements

    Priority MEDIUM
    iyerv
    Jan 15, 2014
  4. handler

    Address 40 sample offset mystery

    Priority MEDIUM
    iyerv
    Jan 15, 2014
  5. handler

    Support IRQ generation from FPGA module to make host event detection less hoggy

    Priority MEDIUM
    iyerv
    Jan 15, 2014
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