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EXPORTED CLOCKS Dialog

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    : Each clock can be enabled/disabled. (CFG setting)
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    : Each clock signal can be phase shifted relative to the true start of frame/line/pixel. Only a positive phase shift (delay) is supported at this time. (CFG setting)
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    : (Only settable for Line Clock at this time). Specifies that clock signal is 'gated' by the parent clock (frame->line and line->pixel are parent/child pairs). Gating is required to prevent clock ticks when acquisition is not active. The default settings should apply for most cases.
    When
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    is selected, the
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    of the parent clock is added to the value for the child clock.
    Enabling
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    for the Line Clock suppresses clock tick for final line if
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    is enabled in the
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    panel. However, this prevents
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    values for Frame and Line clocks from being independent.
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    : Specifies if rising or falling edge signals the start of frame/line/pixel.
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    : Specifies at what fraction of the pixel period to generate the edge not specified by the
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    . Value must be < 1, to allow edge specified by
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    to occur at start of subsequent pixel period. (CFG setting)
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    : If false, the clock signals are only generated during GRAB/LOOP acquisitions, not FOCUS acquisitions. (USR setting)

Settings labeled as CFG settings are considered part of the ScanImage Configuration and saved to CFG files. Different configuration files can save different values of this setting. This is useful, for instance, if you want the frame clock to be exported only for certain experiments, but not others.
Settings labeled as USR settings are considered part of ScanImage User Settings and saved to USR files.

Configuring Exported Clocks in INI File

Each clock output requires a National Instruments counter/timer channel be used. These must be specified in the ScanImage INI file.

Both Board and Counter ID values must be specified – e.g.

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&

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must be specified to enable frame clock feature, etc.

Note that Ctr0 on the primary board (

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) is reserved by ScanImage, and not available for frame/line/pixel clocks

Frame/Line/Pixel 'End' Edge

For the exported clock signals, the edge not specified by

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signifies the 'end' of each Frame/Line/Pixel. The timing/meaning of the 'end' is as follows:

  • Frame/Line Clocks: The 'end' of Frame/Line occurs means acquisition has ended for current frame/line, while acquisition for new frame/line has not begun. This occurs at the start of the scanner flyback or turnaround time at end of line, or end of last line in frame.
  • Pixel Clock: The Pixel clock handling is different because there are no gaps between pixel periods; thus the location of the 'end' edge must be user specified (via Pixel Fraction).

DAQ Board Considerations

The Frame/Line/Pixel clock feature is most powerful with new X series boards. Future ScanImage versions may be able to get more functionality out of other/earlier board families, but this cannot be guaranteed as a development priority.

  • Finite clock generation is only possible with X series boards. When using a non-X series board, additional clock 'ticks' may appear after acquisition is finished, because the counter output is actually stopped in software.
  • Consequently, pixel clock generation – which requires finite clock generation – is only possible with X series boards at this time.
  • X series boards have 4 counter/timer channels, while other board families have only 2 counter/timer channels
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